Webinar: Overcoming DDR Routing Challenges with Advanced PCB Design and DFM Practices
REGISTER NOW
March 11th, 2025 | 10 AM PT
COST: FREE
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1
Day
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1
Hours
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36
Minutes
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20
Seconds
Jerry Long
Senior Applications Engineer, EMA Design Automation
Orlen Bates
Field Applications Engineer, EMA Design Automation
Amit Bahl
CRO, Sierra Circuits
This webinar will be hosted on Zoom.
Following this event, you will receive:
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Presentation slides
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Recording
Webinar abstract:
Designing DDR prototypes? Don’t let DFM issues put your job on hold!
By addressing design for manufacturing (DFM) concerns early in the design phase, such as insufficient annular rings and copper-to-copper clearances, you can avoid delays and expensive board respins.
In this webinar, you’ll learn the best DFM rules for DDR designs. Whether you’re working with DDR3, DDR4, or DDR5, these guidelines will help you create robust high-speed circuit boards.
Essential DFM guidelines for DDR prototypes
Start by collaborating with your fab house early in the design phase. Clearly communicate your design intent and ensure your layout aligns with their capabilities, including trace widths, via sizes, and layer stack-ups.
Choosing the right laminate plays a significant role when designing high-speed PCBs. Ensure the parameters such as glass transition temperature (Tg), thermal conductivity (k), and mechanical strength align with your design needs.
Plan your layer stack-up carefully for optimal signal integrity. Keep DDR signal layers next to a reference plane to reduce crosstalk.
Trace width and spacing are key when routing DDR signals. To minimize crosstalk, keep DDR signals away from other high-speed clock lines and power tracks. Maintain a spacing of at least 3W (‘W’ is the trace width) between adjacent critical signals. Run a DRC to ensure these constraints are met accurately.
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If you’re designing a point-to-point DDR interface, you may not need additional termination. However, for multi-drop configurations, ensure each branch is correctly terminated. For DDR5, on-die termination simplifies your design. For DDR3 and DDR4, employ series resistors near the source and parallel termination at the receiver to minimize impedance mismatches.
Even though vias might introduce signal loss, they are unavoidable in DDR routing. Minimize the via counts in DDR signal lines (preferably 2). Have at least 8 mil clearance between vias and adjacent traces to avoid interference. To ensure reliable plating during manufacturing, keep the aspect ratio 10:1 for through holes and 0.75:1 for microvias.
Solder masks and silkscreen may seem like minor details, but they can impact your design significantly. To prevent solder bridging, use a solder mask with a thickness of around 8-10 microns. Ensure the solder mask clearance around DDR pads is sufficient to avoid masking the pads.
For silkscreen, clearly label DDR components and their orientations. Avoid placing silkscreen text over pads or vias. For better readability, use a font size of at least 25 mil.
Ready to elevate your designs? Sign up for this webinar to gain practical DFM guidelines for DDR prototypes and create reliable high-speed PCBs.
Webinar agenda:
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Design for manufacturing guidelines for DDR prototypes
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Key DFM rules for DDR designs:
- • PCB stack-up
- • Trace width and spacing
- • Length matching and controlled impedance
- • Termination techniques for DDRs
- • Via design clearance and aspect ratio
- • Decoupling capacitor placement near DDR
- • Solder mask and silkscreen
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PCB stack-up created or imported
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Constraint manager
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DDRs techniques for 3, 4 & 5
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Placement
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DFF, DFA and DFT checks
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Signal integrity checks
Jerry Long, Senior Applications Engineer at EMA Design Automation
Jerry A. Long is a Senior Applications Engineer and Product Development Engineer for EMA Design Automation (Rochester, New York) based in Austin, Texas. Jerry provides high-end customer support for several Cadence products, as well as product development and technical marketing guidance for the Timing Designer product. Jerry joined EMA in January 2007 after 7 years with Forte Design Systems and has been involved in several product lines involving verification and timing analysis. Prior to Forte, he served as Member of Technical Staff for Programmable Logic Division of Advance Micro Devices. He holds a bachelors degree in Electrical Engineering from the University of Texas at Austin.
Orlen Bates, Field Applications Engineer at EMA Design Automation
Orlen Bates, Jr. schooling in Drafting and Design started at a Vocational School. He started his career hand taping PCB designs for National Cash Reg. While working for NCR he attended college, and later was transfer to NCR Florida. Went to work for GE Aerospace, and from there as Cad Manager at Jabil Circuits Inc in Michigan. While moving on and working for a Design Service Bureau, when it got sold, he parted ways with them and started his own Design Service Bureau back in Florida, with offices in four states. With a few other stops along the way, started with EMA Design Automation, Inc. as a Field Applications Engineer and Physical Design Consultant and now with EMA for 22 years. Staying in the physical design, Orlen feels it makes him a better Applications Engineer and teacher of the software. The one project he enjoyed the most was Polar, on time, no cost overruns, still working with no reworks.
Amit Bahl, CRO at Sierra Circuits
Amit Bahl, widely recognized as the PCB Guy, currently serves as the Chief Revenue Officer at Sierra Circuits. He earned his Bachelor of Science in Engineering from UCLA in 1997, launching his career in Silicon Valley's tech industry. In 2009, he assumed the role of Director of Sales and Marketing at Sierra Circuits, with a dedicated focus on democratizing design for manufacturing best practices and guidelines for PCB designers and engineers. Assuming the position of Chief Revenue Officer since 2022, Amit's mission persists: to simplify the PCB design journey for all stakeholders. His unwavering dedication continues to drive Sierra Circuits as a trusted resource for the PCB design community.
