How to Route a PCB in KiCad

KiCad is a powerful open-source PCB design tool with advanced routing features to ensure signal integrity, noise reduction, and trace layout optimization.

In this KiCad tutorial, you’ll learn the essential steps to route a PCB. We will cover critical aspects like adding ground pours, managing power routing, handling differential pairs, and applying orthogonal routing techniques.

Understanding the prerequisites for routing in KiCad

Before starting the routing process, ensure the components are placed strategically to simplify the routing process and minimize the need for vias.

During the placement stage, complete the fan-out process, adding all the required vias. This avoids the need for additional vias during the routing phase. By managing this upfront, you’ll make the routing process much smoother and more efficient.

For instance, in this example, you can see that each pin with a net is fanned out. The means the necessary traces and vias are in place.

Fanning out process in a PCB using KiCad.

For tips on efficient component placement, see component placement guidelines for PCB design and assembly.

Step-by-step procedure to route a PCB in KiCad

Step 1: Add a ground pour

Follow these steps to add a ground pour in your layout:

Step 1.1: Select the ground layer

First, ensure you’re working on the correct layer. In this layout, layer 3 is a ground layer.

To select the ground layer, click GND.Cu in the Layers tab under the Appearance section.

Selection of ground layer in KiCad Version 8.

Step 1.2: Add a filled zone

Click on Add Filled Zones in the vertical toolbar or navigate to Place –> Add Filled Zones in the top menu.

Select Add Filled Zone from the right selection panel in KiCad.

Step 1.3: Define the zone area

Before placing the zone, set the grid spacing to help you precisely place and align components and tracks on your layout.

To define the grid spacing, use the drop-down panel and set it to 5 mil.

Grid spacing selected as 5 mil in KiCad.

Maintain at least 20 mil spacing between the board’s edge and the zone. Measure 20 mils from the X and Y axes at the board’s edge and click to begin defining the zone.

Start adding the zone 20 mil away from the board’s edge (X and Y axes).

Step 1.4: Configure copper zone properties

To place the zone, click on your screen. The Copper Zone Properties window will appear.

Copper zone properties window for defining ground pour in KiCad.

Here’s what you need to configure:

Layer: Ensure that GND.Cu is selected.
Net: Choose GND.
Zone name: Optionally, you can name the zone. This can be useful if you set specific rules for this zone in the custom rules section.
Electrical properties:
- Clearance: 15 mil.
- Minimum width: 10 mil.
- Pad connections: Choose Solid for the pad connection, as we’re not using thermal reliefs.
Fill type: Select Solid fill for a complete pour. Hatch fill is typically used for flex PCBs, but for a rigid PCB, solid fill is preferable.
Shape:
- Outline display: Select Hatched for the zone outline display.
- Corner smoothing: Set this to Chamfer for smoother edges.
Remove islands: Enable this option as Always to remove any isolated copper areas after the pour automatically.

Step 1.5: Apply and fill the zone

After configuring these settings, click OK.

Next, select the area you want the ground pour to cover. Once the area is selected, right-click and choose Close Outline. Then, right-click again and select Cancel from the same menu.

Select Close Outline and Cancel to apply ground zone settings.

Click on the ground pour outline you’ve drawn on the PCB layout, select Zones followed by Fill All Zones to complete the ground pour.

Select Zones and choose Fill All Zones to complete the ground pour.

Step 1.6: Review the ground plane

After zone filling, review the third layer. You’ll see that the entire third layer is now covered by the copper ground pour.

The third layer is covered with ground fill.

All ground vias will automatically be connected to this layer.

Ground vias are automatically connected to the ground layer.

This completes the process of adding a ground plane in KiCad.

For step-by-step guidelines on designing a PCB using KiCad, download our eBook.

KiCad Design Guide

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Creating a component symbol library
Setting up board parameters and rules
How to route differential pairs
How to place of components

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Step 2: Implement power routing

The first crucial step in PCB routing is to plan the power distribution.

Step 2.1: Plan your power layers

Determine which layers of the stack-up will be dedicated to power distribution. Select POWER.Cu for power routing.

Step 2.2: Create polygons for VIN, 3.3V, and 5V power nets

3.3V net: Place a polygon for 3.3V on POWER.Cu (layer 2), ensuring that it covers the necessary components. To create the polygon, follow the steps to add filled zones explained in the above section. You need to choose POWER.Cu in the layer section and +3V3 in the net section.

VIN net: For the VIN connection, begin by placing a polygon on the top layer of the PCB since the power layer is already occupied by the 5V net in certain areas.

If the 3.3V polygon on layer 2 blocks the path for VIN, it’s better to route it on the bottom layer. This way, you avoid interference between power nets and ensure that each has sufficient space. After routing 3.3V on layer 2 and VIN on the bottom layer, the two nets can safely overlap without conflicts.

5V net: Once the 3.3V and VIN polygons are placed, you can focus on the 5V net. The 5V net will most likely be routed on the power layer (layer 2) in most designs. Use a polygon on the same power layer to connect all the 5V points, leaving space for the ground around the board’s edges to help with noise suppression.

Polygon created for 5V net in the power layer.

Maintain a 45-degree angle when you draw the polygon edges as a clean design practice. Further, you must maintain proper clearances and ensure the trace fits within the designated space.

Step 2.3: Route the power nets

Route PWR IN and VIN nets on both TOP.Cu (top layer) and POWER.Cu (layer 2) to increase the current-carrying capacity of the traces.

The bottom layer is not used for power routing VIN, as the current requirements (1.5 to 3 amps) are adequately managed by layers 1 and 2.

PWR IN and VIN net routed on layer 1 and layer 2.

To ensure your trace width can handle the expected current, use an online current calculator, taking into account the copper thickness and the current that will flow through the traces.

PCB DESIGN TOOL

Trace Width, Current Capacity and Temperature Rise Calculator

TRY TOOL

Step 2.4: Connect power to components

Next, consider the 5V net, one of the board’s primary power lines. This net, represented by red lines in the design, is routed to multiple components, including the main controller.

Route the 5V net on the top layer and extend this using vias to POWER.Cu (layer 2), similar to the PWR IN and VIN routing strategy.

Step 2.5: Handle lower power nets

For lower power nets like the 3.3V rail, which is generated from the 5V supply, place the voltage regulator close to the source to minimize the routing length.

Route the 3.3V output from the regulator directly to the op-amp located at the bottom of the board. Since this connection involves low current due to the high impedance of the inverting input, a polygon pour is not required. Instead, use a simple trace on the bottom layer.

3.3v-connected-in-pcb-layput.jpg — Trace from the op-amp’s inverted pin to 3.3V via.

To route this, select the Route Tracks from the right-hand toolbar in KiCad. Click on the starting point of your trace on the layout and drag to position it.

If you need to adjust the trace width, press W while routing and set the width to your desired value (15-20 mils in this case). Continue routing until you connect the trace directly to the 3.3V via.

Step 2.6: Ensure proper clearance and ground stitching

As you complete your power routing, always maintain sufficient clearance between adjacent power polygons, especially on the power layers. This allows you to place ground between them, crucial for reducing noise and ensuring stable operation.

Finally, make sure the board’s edges are covered with ground polygons. Use vias to stitch the ground plane across different layers, especially along the board’s edges, to create a robust, noise-resistant design.

By following these steps in KiCad, you can ensure that your PCB’s power routing is efficient and capable of handling the necessary current loads.

Also read: How to Export Gerber and Production Files in Altium Designer

Step 3: Route differential pairs and critical traces

Prioritize routing all differential pairs and critical signal lines before moving on to other traces. This ensures that the most important signals follow the smallest path to minimize the risk of interference.

Step 3.1: Set rules for routing

Before you begin routing, configure the necessary rule settings under Board Setup. These rules will govern the trace widths, spacing, and other constraints to ensure your design meets the required standards.

Click on the **Board Setup** from the top toolbar.

Pay special attention to custom rules and net classes. These settings will dictate the trace widths and gaps, especially for differential pairs.

For example, if you’re working with a differential pair, you might set the differential pair width to 5.5 mil and the gap between the two traces to 4 mil.

Set the differential pair trace width and the gap between the two traces under Net Classes in the Board Setup.

Ensure your minimum track width in the constraint manager is less than or equal to the differential pair width. If this is not set correctly, KiCad may not apply the rules as expected, leading to routing errors.

The minimum track width in the constraint manager should be less than or equal to the differential pair width.

Step 3.2: Route differential pairs

Differential pairs need to be routed with precision to maintain signal integrity. Start by placing the components first so the differential pairs can be routed as straight as possible, avoiding bends.

Make sure all the differential pairs are routed first, as they are critical to the performance of your PCB.

To learn about routing differential pairs, length matching, and skew tuning in KiCad, see how to route differential pairs in KiCad.

Step 3.3: Run design rule checks (DRC)

Once your critical routing is complete, run a design rule check (DRC) in KiCad to ensure all rules, especially those related to differential pairs, have been adhered to. If there are any violations, such as excessive skew between the traces, the DRC will flag these issues, allowing you to correct them before finalizing the design.

Controlling the skew between differential pairs in high-speed PCB designs is crucial to maintaining signal integrity. The new version will introduce advanced skew management features. To learn more, see KiCad version 9: exploring the new features.

Step 4: Execute orthogonal routing

Orthogonal routing involves setting one layer for horizontal traces and the adjacent layer for vertical traces. This method reduces the chances of trace intersections and eliminates the need for additional vias, keeping your design clean and efficient.

Here’s how to do orthogonal routing in KiCad.

Step 4.1: Select the layer for routing

On the right selection pane, choose the TOP.Cu if you want to route on the top layer of the PCB in KiCad. Ensure only the layers you are working with are visible to avoid screen clutter.

Step 4.2: Start the interactive router

To activate the interactive routing tool, press X or select Route Tracks from the toolbar.

Step 4.3: Select track/via width

Begin routing by clicking on the starting pad or via. Right-click to bring up the context menu, then choose Select Track/Via Width.

Click on Trace netclass width to use the predefined width based on the net class settings you configured earlier. This ensures consistent trace widths across your design.

Select Track net class width to use the predefined width based on the configured net class settings.

Step 4.4: Route the traces

Click on the pad or via where the trace will start, usually a component pad. Move your cursor in the direction you want to route the trace. If you need to change directions, simply move the mouse to the new direction; KiCad will adjust the trace accordingly.

Orthogonal routing in PCB using KiCad 8.

Complete the trace by clicking on the pad or via where it ends. If you need to cross over another trace, consider adding a via to route the trace to the opposite side of the board.

To route vertical traces, switch to the Bottom.Cu (bottom layer). This keeps your routing clean and organized.

In the layout below, the top layer showcases horizontal routing highlighted in red, while the bottom layer displays vertical routing, represented in blue.

Orthogonal routing on the top and bottom layer in KiCad.

Step 5: Route the crystal oscillator

Another crucial part of Kicad PCB routing is crystal placement. A crystal is a continuously varying signal required for any microcontroller to operate and used as a reference signal. This should be very close to the microcontroller, and its track should be as short as possible.

Crystal routing in PCB using KiCad version 8.

Follow these steps to route a crystal.

Step 5.1: Place the crystal close to the IC pins

Position the crystal as close as possible to the relevant IC pins. This reduces the trace length and helps maintain signal integrity. While placing the crystal, connect it directly to the IC pins using the interactive routing tool (X key) to ensure the shortest route.

Step 5.2. Position load capacitors near the crystal

Place the load capacitors close to the crystal, preferably on the same layer. If space constraints make this difficult, place them on the bottom layer directly beneath the crystal to keep them close.

Place load capacitors close to the crystal.

Connect the load capacitors to the ground plane through a ground via.

To place a via:

Begin routing a track by selecting the Route Tracks (or shortcut key X)
While routing, press the V key on your keyboard. This automatically places a via at the current cursor position and switches the routing to the next layer in the stack.
Move the cursor to continue routing on the new layer. The via will connect the trace from the current layer to the newly selected layer.
To stop routing, right-click and choose Cancel or press the Esc key.

The aim is to keep the crystal and its load capacitors close to each other and the IC pins to minimize signal degradation.

Step 5.3: Fan out critical power traces

Before finalizing the crystal placement, ensure critical power traces, such as 5V, are properly fanned out with vias.

Place vias to connect power traces to other layers, ensuring power distribution is handled before placing the crystal too close to the IC pins.

Fan out 5V before finalizing crystal placement.

Step 5.4: Optimize the crystal placement

Once the power traces are fanned out, finalize the crystal’s position. Ensure it is close to the IC pins while maintaining enough clearance from power vias.

Always prioritize the placement and routing of crystals and bypass capacitors to ensure stable operation.

After completing the PCB routing in KiCad, check that the designators do not overlap with the differential pairs. It’s acceptable if they overlap with the tracks but not the pairs.

Step 6: Add ground pours on the outer layers

After routing, you must add ground pours on the outer layers. This is essential for providing a low-impedance return path for your signals and improving overall electromagnetic compatibility.

Start by pouring copper on the desired portion of the top and bottom layers. Ensure all pours are complete and consistent.

Maintain sufficient clearance between polygons and traces to avoid unintended interactions, especially around critical impedance traces. Keep a clearance of 15 mil between polygons and 10 mil between polygons and traces.

For high-impedance traces, use a clearance of 5W (five times the trace width) to avoid signal distortion.

Clearance of 5W between impedance traces and polygon.

If maintaining a 5W clearance isn’t feasible, you can reduce it to 3W but avoid going any lower to prevent impedance issues.

If maintaining the required clearance isn’t possible and the copper pours significantly impact the trace impedance, it’s better to avoid pouring copper in those areas altogether.

Step 7: Adjust reference text placement and size

To move the ref text, place the cursor on it, select it, and find a suitable place. Select a proper place so the distance from the ref text is at least 6 mil from the pads.

Click Edit —> Edit Text & Graphic Properties from the menu to change the size. Choose the layer as F.Silkscreen and adjust all the required properties, then click OK.

Edit text and graphic properties dialog box.

You can place your ref text over your vias if they are tented, which means they will be covered with the solder mask. Always keep ref text away from the pads and the vias. If it is impossible to keep it away from your vias, then tent your vias.

Step 8: Run design rules checker (DRC)

Let’s complete the entire placing of the ref text before starting with the DRC. Make sure that all the ref texts are away from the pins. Once this is done, you can run a DRC.

This will check whether those rules are being followed or not. It ensures no violations, such as overlapping traces or too-close clearances.

So, let’s see how it works. Save this and go to Inspect and Design Rules Checker. This is the minimum track width as per the DRC.

To create a report file:

Step 8.1: Navigate to Inspect > Design Rules Checker.